1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to an apparatus for storing a data value, such as, for example, a latch or a flip-flop, which has a retention mode of operation in which the data value is retained but a lower level of power is consumed.
2. Description of the Prior Art
It is known to adapt data processing apparatus in the form of integrated circuits to reduce the power consumed. One way of achieving this is to provide a retention mode in to which the apparatus may be placed when it is not desired to perform data processing operations while retaining the data and state currently held within the integrated circuit. The power consumed in the retention mode may be significantly reduced compared to the power consumed in the functional mode when the integrated circuit is actively performing data processing operations.
As the device size geometries decrease within integrated circuits, a significant problem that arises is the power consumed due to leakage currents. Such leakage currents arise even when the integrated circuit is in a retention mode in which active data processing is not performed. In order to address the problems of leakage current, it is known to utilise power gating. In power gating a portion of an integrated circuit may be isolated from the power supply during a retention mode so as to reduce the leakage current through that portion. A problem with power gating is that the time taken to restart processing operations may be comparatively large as the signal nodes and power/signal lines within the portion of the integrated circuit which has been isolated from the power supply will need to recharge to their starting levels before processing can be restarted. Furthermore, there may be problems such as crowbar currents in which a significant amount of power is consumed by gates pulling single nodes in opposite directions until a proper starting state has been reached.
One way of dealing with these problems within integrated circuits using power gating is to provide what is termed “zig-zag” power gating. Zig-zag power gating is a leakage mitigation technique where a predetermined logic state (sleep vector) is applied to a design in the retention mode and then all leaking pull up/pull down stacks of gates are disconnected from one of the power or ground using distributed power gates. The signal nodes are maintained at their proper values as they remain connected to the appropriate power rail (either power or ground), but the leaking pull up or pull down stacks are disconnected from one of the power rails thereby reducing leakage through the stack. This allows for a quicker turn on time since the logic levels are maintained. Furthermore, as no charging or discharging of nodes or signal capacitances is required, and no crowbar currents arise, power consumption upon start up is reduced.
In order to force the portion of the integrated circuit being subject to the zig-zag power gating in to the appropriate state corresponding to the sleep vector, both state retention devices (latches, flops etc.) and primary inputs should be controllable. Primary inputs may be controlled by the insertion of isolation/clamp cells at the power domain boundary. State retention devices may be controlled to produce known outputs by the use of a NAND/NOR gate on their output and controlled using a state retention signal. Such a NAND/NOR gate may be placed inside the state retention device itself.
Using the above techniques a state retention device may be placed in to a state matching the sleep vector. However, the input to the state retention device may be either 1 or 0, depending upon the upstream circuitry and the data value to be stored by the state retention device during the retention mode may also be 1 or 0. A known way of dealing with this problem is to provide four variants of the state retention device. The variants respectively correspond to the inputs being either 1 or 0 and the output corresponding to the stored data value being forced to either 1 or 0. A significant problem with this approach is that it increased the number of variants of the state retention devices required within a cell library from which an integrated circuit design is assembled. Each of these variants requires separate design, characterisation and testing. This impairs the usefulness of zig-zag power gating as a leakage mitigation technique.